Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell holds a certain level of a given physical quantity such as an electrical charge or voltage, which represents the data stored in the cell. The levels of this physical quantity are also referred to as storage values or analog values. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to a programming state that represents one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some memory devices, which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
The reaction of analog memory cells to programming signals sometimes varies from one memory cell to another. Some known methods and systems program memory cells differently, depending on the cells' responsiveness to programming. For example, U.S. Pat. No. 7,177,199, whose disclosure is incorporated herein by reference, describes a process for programming a set of non-volatile memory cells, which is adapted based on behavior of the memory cells. In an example process, a set of program pulses is applied to a set of Flash memory cells. A determination is made as to which memory cells are easier to program and which memory cells are harder to program. Bit line voltages or other parameters are adjusted based on the determination. The programming process then continues with the adjusted bit line voltages or other parameters.
U.S. Pat. No. 6,166,962, whose disclosure is incorporated herein by reference, describes a circuit and method for equalizing charge-discharge characteristics of an array of Flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, and leaves other cells relatively unaffected so that the fast bits are adjusted to have threshold voltages closer to those of the other cells in an array. In this manner, the voltage thresholds are tightened and equalized.
U.S. Pat. No. 7,408,804, whose disclosure is incorporated herein by reference, describes systems for soft programming of non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells. A set of non-volatile storage elements is divided into subsets in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed. After the set is verified as soft programmed, a first subset of elements is inhibited from further soft programming while additional soft programming is carried out on a second subset of elements. The second subset may include slower soft programming elements. The second subset can then undergo soft programming verification while excluding the first subset from verification. Soft programming and verifying for the second subset can continue until it is verified as soft programmed.
U.S. Pat. No. 5,751,637, whose disclosure is incorporated herein by reference, describes a programming method for page mode Flash memory with variable programming pulse height and pulse width. The method provides a pattern of program retry pulses which have respective pulse widths and pulse heights, which vary according to a pattern. The pattern includes a combination of both increasing pulse widths and increasing pulse heights. The pattern includes a first phase which completes in a specified amount of time including a predetermined number of retries so that substantially all of the cells in the array are programmed within the first phase. A second phase of the patter involves a sequence of higher-energy pulses addressed to programming the slowest cells in the array.
U.S. Pat. No. 7,139,192, whose disclosure is incorporated herein by reference, describes write operations that simultaneously program multiple memory cells on the same word line in a multi-level non-volatile memory. The write operations employ word line voltage variation, programming pulse width variation and column line voltage variation to achieve uniform programming accuracy across a range of target threshold voltages. During or at the end of write operations, remedial programming sequences can adjust the threshold voltages of memory cells that program slowly.